Thermally Enhanced Three-Dimensional Package and Method for Manufacturing the Same

ABSTRACT

A thermally enhanced three-dimensional (3D) package is disclosed. The package includes a heat sink having an opening and a stiffener ring inside the opening. The stiffener ring has a first surface and a second surface. A first substrate of a first package is disposed inside the opening and secured to the first surface of the stiffener ring. A second substrate of a second chip package is secured to the second surface of the stiffener ring. The first substrate is connected to the second substrate through a plurality of solder balls. The heat generated in the first chip package and the second chip package is dissipated by the heat sink. The first chip package and the second chip package are fixed by the stiffener ring to eliminate warpage of the first chip package and the second chip package, thereby assuring the electrical transmission of the product.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 11/164,819filed Dec. 7, 2005, and incorporated herein by reference in itsentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a thermally enhanced three-dimensional package,and more particularly, to a three dimensional package utilizing a heatsink on a first chip package to position another chip package.

2. Description of the Prior Art

In conventional semiconductor packages, three dimensional packagesfabricated by stacking a plurality of chip packages over one another arecommonly utilized to achieve multi-functional purpose. However, as thechip packages generate large amounts of heat during operation, a heatsink is often installed to maintain the three dimensional package at anormal working temperature. Additionally, a boat is utilized to positionthe chip packages while stacking the chip packages over one another.This will unavoidably increase the overall cost. Moreover, a slightmiscalculation in the size of the boat or the edge of the substrate ofthe chip packages will result in a cold joint issue and unsuccessfulbonding of the chip package, and as the chip packages undergo numerousreflow processes, a warpage phenomenon will often result.

Please refer to FIG. 1. FIG. 1 is a perspective diagram showing across-section of a conventional three-dimensional package. As shown inFIG. 1, the three-dimensional package 100 includes a first chip package110, a second chip package 120, a plurality of solder balls 130, and aplurality of external conductive devices 140. Preferably, the first chippackage 110 includes a first substrate 111 and a first flip chip 112, inwhich the first substrate 111 includes a top surface 113 and a bottomsurface 114. The flip chip 112 is connected to the bottom surface 114 ofthe first substrate 111 by utilizing a plurality of bumps 115, in whichthe bumps 115 are sealed by an underfill layer 116. Similarly, thesecond chip package 120 includes a second substrate 121 and a secondflip chip 122, in which the second substrate 121 includes a top surface123 and a bottom surface 124. The second flip chip 122 is connected tothe top surface 123 of the second substrate 121 by utilizing a pluralityof bumps 125, in which the bumps 125 are sealed by an underfill layer126. Additionally, the solder balls 130 are formed between the topsurface 113 of the first substrate 111 and the bottom surface 124 of thesecond substrate 121 to electrically connect the first chip package 110and the second chip package 120, and the external conductive devices 140are disposed on the bottom surface 114 of the first substrate 111 forconnecting to other electronic devices (not shown).

Essentially, the first chip package 110 and the second chip package 120of the three-dimensional package 100 often generate significant amountsof heat during operation thereto reducing the performance of the deviceas a result of overheating. Additionally, phenomenon such as warpageoccurs frequently on the first chip package 110 and the second chippackage 120 and influences the structural sturdiness and electricaltransmission of the three-dimensional package 100. Furthermore, when thefirst chip package 110 and the second chip package 120 are stacked overeach other, a boat is commonly utilized to position the first chippackage 110 and the second chip package 120, thereby increasing cost andreducing over yield.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provided athermally enhanced three-dimensional package. Preferably, the thermallyenhanced three-dimensional package includes a heat sink, a first chippackage, and a second chip package, in which the heat sink includes anopening and a stiffener ring inside the opening. A first substrate ofthe first chip package is positioned in the opening and secured on afirst surface of the stiffener ring, and a second substrate of thesecond chip package is secured on a second surface of the stiffenerring. By utilizing the stiffener ring to secure the first chip packageand the second chip package, the present invention is able to preventthe warpage phenomenon of the first chip package and the second chippackage.

It is another aspect of the present invention to provide a thermallyenhanced three-dimensional package. Preferably, the thermally enhancedthree-dimensional package includes a heat sink having an opening and astiffener ring inside the opening, a first chip package disposed on afirst surface of the stiffener ring, and a second chip package disposedon a second surface of the stiffener ring, such that the heat generatedby the first chip package and the second chip package during operationcan be dissipated via the heat sink.

It is another aspect of the present invention to provide a thermallyenhanced three-dimensional package. Preferably, the thermally enhancedthree-dimensional package includes a heat sink having an opening and astiffener ring inside the opening, a first chip package disposed on afirst surface of the stiffener ring, and a second chip package disposedon a second surface of the stiffener ring, in which the stiffener ringis utilized to control the height of the solder balls between the firstchip package and the second chip package, thereby preventing a solderfailure or a broken circuit.

It is another aspect of the present invention to provide a method offabricating a thermally enhanced three dimensional package, the methodincludes: providing a first chip package, wherein the first chip packagecomprises a first substrate; disposing a heat sink having a firstopening and a stiffener ring inside the first opening on the first chippackage, wherein the stiffener ring comprises a first surface and asecond surface and the first substrate of the first chip package isdisposed in the opening of the heat sink and secured to the firstsurface of the stiffener ring; disposing a second chip package having asecond substrate on the heat sink, wherein the second substrate issecured to the second surface of the stiffener ring; and performing areflow process for forming a plurality of solder balls between the firstsubstrate and the second substrate, wherein the solder balls are formedinside the stiffener ring for connecting the first substrate and thesecond substrate.

According to the present invention, a thermally enhanced threedimensional package includes: a heat sink having a first opening and astiffener ring inside the opening, in which the stiffener ring comprisesa first surface and a second surface; a first chip package having afirst substrate, in which the first substrate is disposed in the openingof the heat sink and secured to the first surface of the stiffener ring;a second chip package having a second substrate, in which the secondsubstrate is secured to the second surface of the stiffener ring; and aplurality of solder balls disposed between the first substrate of thefirst chip package and the second substrate of the second chip packageand inside the stiffener ring for connecting the first substrate and thesecond substrate. Preferably, the heat sink is utilized to position andfacilitate the stacking of the first chip package and the second chippackage, and the stiffener ring is utilized to secure the first chippackage and the second chip package for preventing a warpage phenomenonand facilitating the heat dissipation of the two package structures.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective diagram showing a cross-section of aconventional three-dimensional package.

FIG. 2 is a perspective diagram showing the cross-section of a thermallyenhanced three-dimensional package according to the first embodiment ofthe present invention.

FIG. 3 is a three-dimensional diagram showing the heat sink of FIG. 2.

FIG. 4 through FIG. 6 are perspective diagrams showing a means offabricating the thermally enhanced three-dimensional package 200according to the first embodiment of the present invention.

FIG. 7 is a perspective diagram showing the cross-section of a thermallyenhanced three-dimensional package according to the second embodiment ofthe present invention.

FIG. 8 is a perspective diagram showing the cross-section of a thermallyenhanced three-dimensional package according to the third embodiment ofthe present invention.

FIG. 9 is a perspective diagram showing the cross-section of a thermallyenhanced three-dimensional package according to the fourth embodiment ofthe present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2 and FIG. 3. FIG. 2 is a perspective diagramshowing the cross-section of a thermally enhanced three-dimensionalpackage according to the first embodiment of the present invention andFIG. 3 is a three-dimensional diagram showing the heat sink from FIG. 2.As shown in FIG. 2 and FIG. 3, a thermally enhanced three-dimensionalpackage 200 includes a heat sink 210, a first chip package 220, a secondchip package 230, and a plurality of solder balls 240. Preferably, theheat sink 210 includes an I-shaped cross-section, an opening 211, and astiffener ring 212 inside the opening 211, in which the stiffener ring212 is monolithically formed on the heat sink 210. Additionally, thestiffener ring 212 includes a first surface 213 and a second surface214, such that the opening 211 exposes the first surface 213 and thesecond surface 214. The first chip package 220 includes a firstsubstrate 221 having a top surface 222 and a bottom surface 223, inwhich the first substrate 221 is disposed in the opening 211 of the heatsink 210 and secured to the first surface 213 of the stiffener ring 212by utilizing an adhesive 250, thereby preventing the first substrate 221of the first chip package 220 from suffering from the warpagephenomenon. The first chip package 220 also includes a first chip 224and a plurality of bumps 225. According to the present embodiment, thefirst chip 224 is connected to the bottom surface 223 of the firstsubstrate 221 by a flip chip packaging process, the bumps 225 areelectrically connected to the bottom surface 223 of the first substrate221, and an underfill layer 226 is formed to seal the bumps 225.Additionally, the thermally enhanced three-dimensional package 230includes a plurality of external conductive devices 260, such as solderballs or pins, in which the external conductive devices 260 are disposedon the bottom surface 223 of the first substrate 221 and exposed fromthe opening 211 of the heat sink 210 to provide an external connectionto other electronic devices (not shown).

The second chip package 230 includes a second substrate 231 having a topsurface 232 and a bottom surface 233. Preferably, the second substrate231 is disposed on the second surface 214 of the stiffener ring 212, inwhich the second substrate 231 is secured to the second surface 214 byanother adhesive 250 for preventing warpage of the second substrate 231.The second chip package 230 also includes a second chip 234, such as aflip chip and a plurality of bumps 235, in which the second chip 234 iselectrically connected to the top surface 232 of the second substrate231 by utilizing the bumps 235, and an underfill layer 236 is formed toseal the bumps 235 thereafter.

The solder balls 240 are formed between the first substrate 221 of thefirst chip package 220 and the second substrate 231 of the second chippackage 230 and inside the stiffener ring 212 of the heat sink 210, suchthat the solder balls 240 are utilized to connect the first substrate221 and the second substrate 231, and facilitate the stacking of thefirst chip package 220 and the second chip package 230. Preferably, theheight of the solder balls 240 can be adjusted via the stiffener ring212, thereby preventing a solder failure or a broken circuit.

By utilizing the heat sink 210 to position the first chip package 220and the second chip package 230, the present invention requires noadditional boat as in the prior art. Additionally, the first chippackage 220 and the second chip package 230 are secured on the stiffenerring 212 to prevent the warpage phenomenon. Furthermore, the heatgenerated by the first chip package 220 and the second chip package 230during operation can be transmitted via the first substrate 221 of thefirst chip package 220, the second substrate 231 of the second chippackage 230, and the stiffener ring 212 to the heat sink 210, such thatthe heat will be dissipated by the heat sink 210.

Please refer to FIG. 4 through FIG. 6. FIG. 4 through FIG. 6 areperspective diagrams showing a means of fabricating the thermallyenhanced three-dimensional package 200 according to the first embodimentof the present invention. As shown in FIG. 4, a first chip package 220having a first substrate 221 and a first chip 224 is first provided.Preferably, the first substrate 221 includes a top surface 222 and abottom surface 223, in which the first chip 224 is attached to thebottom surface 223 of the first substrate 221 by utilizing a pluralityof bumps 225. Next, a plurality of solder bumps 240 a is formed on thetop surface 222 of the first substrate 221.

As shown in FIG. 5, a heat sink 210, such as the one shown in FIG. 3, isdisposed on the top surface 222 of the first chip package 220.Preferably, the heat sink 210 includes an opening 211 and a stiffenerring 212 inside the opening 211, in which the stiffener ring 212includes a first surface 213 and a second surface 214. Subsequently, anadhesive 250 is applied on the stiffener ring 212 for attaching thefirst substrate 221 on the first surface 213 of the stiffener ring 212.

As shown in FIG. 6, a second chip package 230 having a second substrate231 and a second chip 234 is disposed on the stiffener ring 212 of theheat sink 210. Preferably, the second chip package 230 includes a secondsubstrate 231 and a second chip 234, in which the second chip 234 isconnected to the top surface 232 of the second substrate 231 byutilizing the plurality of bumps 235. Additionally, an adhesive 250 isformed to attach the second chip package 230 on the second surface 214of the stiffener ring 212, and a plurality of second solder bumps 240 bis formed on the bottom surface 233 of the second substrate 231.Preferably, the heat sink 210 is utilized to position the first chippackage 220 and the second chip package 230, such that the second solderbumps 240 b of the second chip package 230 can be aligned correspondingto the first solder bumps 240 a of the first chip package 220.Subsequently, a soldering flux 270 is formed on the first solder bumps240 a or the second solder bumps 240 b to facilitate the melting of thefirst solder bumps 240 a and the second solder bumps 240 b during areflow process for producing a plurality of solder balls 240 (as shownin FIG. 2). Preferably, the height of the stiffener ring 212 of the heatsink 210 is controlled corresponding to the height of the solder balls240 between the first chip package 220 and the second chip package 230to prevent a solder failure or a broken circuit. Subsequently, aplurality of external conducting devices 260 is disposed on the bottomsurface 223 of the first substrate 221 and exposed from the opening 211of the heat sink 210 for forming a thermally enhanced three-dimensionalpackage 200 (as shown in FIG. 2).

Please refer to FIG. 7. FIG. 7 is a perspective diagram showing thecross-section of a thermally enhanced three-dimensional package 300according to the second embodiment of the present invention. As shown inFIG. 7, the thermally enhanced three-dimensional package 300 includes aheat sink 310, a first chip package 320, a second chip package 330, anda plurality of solder balls 340, in which the heat sink 310 includes anopening 311 and a stiffener ring 312 inside the opening 311. Accordingto the present embodiment, the stiffener ring 312 is step-shaped, inwhich the stiffener ring 312 also includes a first surface 313 and asecond surface 314, and both the first surface 313 and the secondsurface 314 expose the opening 311. Preferably, the first chip package320 is disposed in the opening 311, in which the first chip package 320includes a first substrate 321 and a first chip 324. Additionally, thefirst substrate includes a top surface 322 and a bottom surface 323, inwhich the first substrate 321 is positioned in the opening 311 of theheat sink 310 and secured on the first surface 313 of the stiffener ring310. The first chip 322 is connected to the bottom surface 323 of thefirst substrate 321 by utilizing a plurality of bumps 325, and anunderfill layer 326 is formed to seal the bumps 325.

The second chip package 330 includes a second substrate 331 and a secondchip 334. Preferably, the second substrate 331 includes a top surface332 and a bottom surface 333, in which the second substrate 331 isdisposed in the opening 311 of the heat sink 310 and secured on thesecond surface 314 of the stiffener ring 312. The second chip 334 isattached to the top surface 332 of the second substrate 314 by utilizinga plurality of bumps 335, and an underfill layer 336 is formed to sealthe bumps 335. The solder balls 340 are disposed between the top surface322 of the first substrate 321 and the bottom surface 333 of the secondsubstrate 331, the first chip package 320 is secured on the firstsurface 313 of the stiffener ring 312, and the second chip package 330is secured on the second surface 314 of the stiffener ring 312 tofacilitate the alignment of the first chip package 320 and the secondchip package 330 while stacking the packages over each other.Preferably, the present invention is able to utilize the stiffener ring313 to secure the first chip package 320 and the second chip package 330to prevent warpage of the two packages, utilize the heat sink 310 of thestiffener ring 312 to dissipate heat, and utilize the step-shapedstiffener ring 312 to control the height of the solder balls 340 betweenthe first chip package 320 and the second chip package 330 forpreventing a solder failure or a broken circuit.

Please refer to FIG. 8. FIG. 8 is a perspective diagram showing thecross-section of a thermally enhanced three-dimensional package 400according to the third embodiment of the present invention. As shown inFIG. 8, the thermally enhanced three-dimensional package 400 includes aheat sink 410, a first chip package 420, a second chip package 430, anda plurality of solder balls 440. Preferably, the heat sink 410 includesan opening 411 and a stiffener ring 412 inside the opening 411, in whichthe stiffener ring 412 includes a first surface 413 and a second surface414, such that the first surface 413 and the second surface 414 exposethe opening 411.

The first chip package 420 includes a first substrate 421, a first chip422, a plurality of wires 423, and a sealing compound 424, in which thefirst substrate 421 includes a top surface 425 and a bottom surface 426.The first chip 422 is disposed on the top surface 425, in which thefirst chip 422 is electrically connected to the first substrate 421 viathe wires 423, and the sealing compound 424 is utilized to seal thefirst chip 422 and the wires 425. Preferably, the first substrate 421 iscontained in the opening 411 of the heat sink 410 and secured to thefirst surface 413 of the stiffener ring 412, in which an adhesive 450 isdisposed to secure the bonding of the stiffener ring 412 and the firstsubstrate 421 and prevent warpage of the first substrate 421.Additionally, the thermally enhanced three-dimensional package 400includes a plurality of external conductive devices 460, such as solderballs. As shown in FIG. 8, the external conductive devices 460 aredisposed on the bottom surface 426 of the first substrate 421 andexposed from the opening 411 of the heat sink 410.

The second chip package 430 includes a second substrate 431, a secondchip 432, a plurality of wires 433, and a sealing compound 434, in whichthe second substrate 431 includes a top surface 435 and a bottom surface436. The second chip 432 is disposed on the top surface 435 of thesecond substrate 431 and electrically connected to the second substrate431 via the wires 433, and the sealing compound 434 is formed on the topsurface 435 of the second substrate 431 to seal and protect the secondchip 432 and the wires 433. The second substrate 431 is secured on thesecond surface 414 of the stiffener ring 412, in which an adhesive 450is disposed on the second surface 414 of the stiffener ring 412 toprevent the second substrate 431 of the second chip package 430 fromsuffering from the warpage phenomenon.

The solder balls 440 are formed between the top surface 425 of the firstsubstrate 421 and the bottom surface 436 of the second substrate 431 andon the periphery of the first chip 422, in which the solder balls 440are utilized to electrically connect the first substrate 421 and thesecond substrate 431. Preferably, the thermally enhancedthree-dimensional package 400 is able to utilize the stiffener ring 412to control the height of the solder balls 440 to prevent a solderfailure or a broken circuit, and utilize the heat sink 410 to dissipatethe heat generated during the operation of the first chip package 420and the second chip package 430.

Please refer to FIG. 9. FIG. 9 is a perspective diagram showing thecross-section of a thermally enhanced three-dimensional package 500according to the fourth embodiment of the present invention. As shown inFIG. 9, the thermally enhanced three-dimensional package 500 includes aheat sink 510, a first chip package 520, a second chip package 530, anda plurality of solder balls 540, in which the heat sink 510 includes anopening 511 and a first surface 512 and a second surface 513 inside theopening 511. According to the present embodiment, the opening 511exposes the first surface 512 and the second surface 513 and forms astep shape.

The first chip package 520 includes a first substrate 521, a first chip522, a plurality of wires 523, and a sealing compound 524, in which thefirs substrate 521 includes a top surface 525 and a bottom surface 526.The first chip 522 is disposed on the top surface 525 of the firstsubstrate 521 and electrically connected to the first substrate 521 viathe wires 523, in which the sealing compound 524 is utilized to seal thefirst chip 521 and the wires 523. When the first chip package 520 isbonded to the heat sink 510, the first substrate 521 is positioned onthe first surface 512 of the heat sink 510. Additionally, a plurality ofexternal conductive devices 550 is disposed on the bottom surface 526 ofthe first substrate 521 and exposed from the opening 511 of the heatsink 510 for connecting to other electronic devices (not shown).

The second chip package 530 includes a second substrate 531, a secondchip 532, a plurality of wires 533, and a sealing compound 534. Thesecond chip 532 is disposed on a top surface 535 of the second substrate531, the wires 533 are utilized to electrically connect the secondsubstrate 531 and the second chip 532, and the sealing compound 534 isformed to seal the second chip 532 and the wires 533. When the secondchip package 530 is bonded to the heat sink 510, the second substrate531 is disposed on the second surface 513 of the heat sink 510. Sincethe first chip package 520 is secured to the first surface 512 of theheat sink 510 and the second chip package 530 is secured to the secondsurface 513 of the heat sink 510, the present invention is able toaccurately align and stack the packages over each other, therebypreventing the warpage phenomenon and utilizing the heat sinkeffectively. Additionally, by controlling the height of the heat sink510 corresponding to the height of the solder balls 540 between thefirst chip package 520 and the second chip package 530, the presentinvention is able to prevent a solder failure or a broken circuit.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A thermally enhanced three-dimensional package comprising: a heatsink having an opening, and a first surface and a second surface in theopening; a first chip package having a first substrate, wherein thefirst substrate is secured to the first surface; a second chip packagehaving a second substrate, wherein the second substrate is secured tothe second surface; and a plurality of solder balls connected to thefirst chip package and the second chip package, wherein the first chippackage and the second chip package are stacked over each other.
 2. Thethermally enhanced three-dimensional package of claim 1, wherein theopening of the heat sink comprises a step shape.
 3. The thermallyenhanced three-dimensional package of claim 1, wherein the first chippackage comprises a first chip electrically connected to the firstsubstrate.
 4. The thermally enhanced three-dimensional package of claim1 further comprising a plurality of external conductive devices disposedon the first substrate of the first chip package.
 5. The thermallyenhanced three-dimensional package of claim 4, wherein the externalconductive devices are exposed from the opening of the heat sink.
 6. Thethermally enhanced three-dimensional package of claim 1, wherein thesecond chip package comprises a second chip electrically connected tothe second substrate.